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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC33884/D
Advance Information Switch Monitor Interface
The MC33884 Switch Monitor Interface is a monolithic silicon integrated circuit (IC) that performs switch monitoring functions. The device provides efficient interface between electrical switches and low voltage microprocessors. The MC33884 supplies switch contact pull-up and pull-down current while monitoring the input voltage level. All inputs are protected for transients when implemented with an appropriate static discharge capacitor used on the inputs. There are four modes of operation - Sleep, Normal, Polling, and Polling + INT Timer. Sleep mode reduces the current drain to a quiescent current level of 10 mA and disables the IC. Normal mode interrupts the microprocessor whenever any external switch changes it's OPEN or CLOSED state. Polling mode reads a switch status periodically and interrupts the microprocessor only when an external switch is sensed as being CLOSED. The Polling + INT Timer mode is similar to the Polling mode, with the addition of an interrupt being sent to the microprocessor if a switch is sensed CLOSED or upon the internal interrupt timer "timing out". An interrupt is always ultimately sent to the microprocessor in this mode. All modes of operation are easily programmed via the Serial Peripheral Interface (SPI) control. The MC33884 has the following features: * Full Operation with 7.0 V VPWR 26 V, Limited Operation with 5.5 V VPWR 7.0 V * Input Voltage Range: -14 V to 40 V * Interfaces Directly to Microprocessors Using SPI Protocol * 24-Lead Wide Body SOIC Package * Wake-up on Change of Monitored Switch Status * Programmable Wetting Current * 4 Programmable Inputs to Monitor 4 Switch-to-Battery or 4 Switch-to-Ground Switches * 6 (fixed function) Inputs to Monitor 6 Switch-to-Ground Switches * 2 (fixed function) Inputs to Monitor 2 Switch-to-Battery Switches * Standby Current During Normal Mode = 100 mA * Quiescent Current in Sleep Mode < 10 mA * Reset (RST) Input Defaults the Device to Sleep Mode * Active Interrupt (INT) on Change of Switch State in Normal Mode * 4 Modes of Operation (Sleep, Normal, Polling, Polling + INT Timer) * Designed to Operate -40C TA 105C
MC33884
SCALE 1:1 DW Suffix 24 Lead SOIC CASE 751E
PIN CONNECTIONS
VDD SO SI SP1 SG1 SG2 SG3 SB1 SP2 MASL VPWR GND
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
SCLK CSB VBG SP4 SG6 SG5 SG4 SB2 SP3 INTB SYNC RSTB
ORDERING INFORMATION
Device MC33884DW MC33884DWR2 Operating Temperature Range TA = - 40 to 105C TA = - 40 to 105C Package SO-24 SO-24
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2 09/01
(c) Motorola, Inc. 2001
t
MC33884
SP1 SP2 SP3 SP4
Switch-to-Ground and Switch-to-Battery Sense Inputs (x4)
Programmable Input Blocks (1-4)
Metallic or Non-metallic Enable or Disable Input Block (Tri-State)
SG1 SG2 SG3 SG4 SG5 SG6
Switch-to-Ground Sense Inputs (x6)
Fixed Input Blocks GND (1-6)
Switch-Ground, Metallic or Non-metallic, Enable or Disable FIB (Tri-State)
SPI Decode
PIB Configure, FIB/PIB Tri-State FIB/PIB Metallic
SB1 SB2
Switch-to-Battery Sense Inputs (x2)
Fixed Input Blocks Battery (1-2)
Switch-Batt, Metallic or Non-metallic, Enable or Disable FIB (Tri-State)
SPI Interface
CSB SI SO SCLK
SPI Encode
Mode Switch Status Quiescent Current Control
V DD VPWR V SS
VDD, V+ Distribution
(To all input blocks)
Mode Control
Normal, Polling, Sleep
INTB
Polling Mode
V BG
Oscillator
Wake-up Slave Sync Master/Slave Select
RSTB
SYNC MASL
Figure 1. Internal Block Diagram
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MOTOROLA TSG IC DEVICE DATA
MC33884
External Switches
V PWR V DD SB1 V PWR
10 nF 0805 100 V 10 nF 0805 100 V
V BAT T V BAT T V BAT T
SB2
10 nF 0805 100 V 10 nF 0805 100 V
V DD
SP1
MC33884
SI
10 nF 0805 100 V
MC68HCXX Microcontroller
10k 0805
16 Bit Shift Register
M S B L S B
V BAT T SP2 V BAT T
10 nF 0805 100 V
MOSI MISO
SO SCLK
SP3 V BAT T
10 nF 0805 100 V
INTB CSB
Parallel Ports
SP4
10 nF 0805 100 V 10 nF 0805 100 V 10 nF 0805 100 V
V BG SG1
130k 0805
RESET
SG2
SG3
10 nF 0805 100 V 10 nF 0805 100 V
10k 0805 RSTB
SG4
WDOG LVI RESET Control
SG5
10 nF 0805 100 V
MASTER NODE
MASL SYNC
SG6 V BAT T V BAT T V BAT T
10 nF 0805 100 V
SB1
10 nF 0805 100 V
SYNC SLAVE NODE V PWR
10 nF 0805 100 V
SB2
10 nF 0805 100 V 10 nF 0805 100 V
SP1
MC33884
V DD
10 nF 0805 100 V
V BAT T SP2 V BAT T
10 nF 0805 100 V
SP3 V BAT T
10 nF 0805 100 V
SI SO SCLK INTB CSB RSTB MASL V BG
SP4
10 nF 0805 100 V 130k 0805
Figure 2. Typical Master / Slave Application
MOTOROLA TSG IC DEVICE DATA
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MC33884
Pin Function Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name VDD SO SI SP1 SG1 SG2 SG3 SB1 SP2 MASL VPWR VSS RSTB SYNC INTB SP3 SB2 SG4 SG5 SG6 SP4 VBG CSB SCLK 5.0 V Logic Supply SPI Data Out Pin SPI Data In Pin Programmable - Switch-to-Battery or Switch-to-Ground Input 1 (Source or Sink Output) Switch-to-Ground Input 1 (Source Output) Switch-to-Ground Input 2 (Source Output) Switch-to-Ground Input 3 (Source Output) Switch-to-Battery Input 1 (Sink Output) Programmable - Switch-to-Battery or Switch-to-Ground Input 2 (Source or SInk Output) Master or Slave Select Pin - Used when multiple MC33884 devices are required in Module Conditioned Battery Supply Voltage Ground Reset Input Synchronization Output - Used when multiple MC33884 devices are required in Module. Provide synchronized wake-up of multiple MC33884 devices. Interrupt - Open Drain Output Programmable - Switch-to-Battery or Switch-to-Ground Input 3 (Source or Sink Output) Switch-to-Battery Input 2 (Sink Output) Switch-to-Ground Input 4 (Source Output) Switch-to-Ground Input 5 (Source Output) Switch-to-Ground Input 6 (Source Output) Programmable - Switch-to-Battery or Switch-to-Ground Input 4 (Source or Sink Output) Bandgap Voltage. A bandgap reference is used to set up the reference and bias currents for the device. A resistor must be connected from this pin to ground. Chip Select Input. Input with internal active pull-up. Requires 5.0 V CMOS logic levels. Communication with the device using SPI is enabled when the CSB pin is a logic 0. Serial Clock. SCLK is used to shift data into and out of the device. It transitions 1 time per bit with an operation frequency, fSCLK, with a 50% duty cycle. SCLK is idle between commands and should be commanded low. Description
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MC33884
MAXIMUM RATINGS (All voltages are with respect to ground, unless otherwise noted)
Rating VDD Supply Voltage CSB, SI, SO, SCLK, RSTB, MASL, SYNC, INTB (Note 1) VPWR Supply Voltage (Note 1) Switch Input Voltage Range Recommended Frequency of SPI Operation ESD Voltage (Note 2) Human Body Model (Notes 3, 4, 5) Machine Model (Note 6) Storage Temperature Operating Case Temperature Operating Junction Temperature Lead Soldering Temperature (Note 7) Maximum Junction Temperature Thermal Resistance, Junction-to-Ambient Plastic Package, 24 SOIC, Case 751E: Symbol - - - - - VESD1 VESD2 Tstg TC TJ TSolder - PqJA Value -0.3 to 7.0 -0.3 to 7.0 -16 to 50 -14 to 40 3.0 4000 200 -55 to 150 -40 to 105 -40 to 150 260 -40 to 150 107 Unit VDC VDC VDC VDC MHz V C C C C C C/W
NOTES: 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. ESD data available upon request. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 4. All pins when tested individually. 5. 1 kV on VPWR and VDD when connected together. 6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 100 pF, RZAP = 0 W). 7. Lead soldering temperature limit is for 10 seconds maximum duration.
W).
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MC33884
STATIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 105C, unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.)
Characteristic Symbol Min Typ Max Units
POWER INPUT
Supply Voltage Range Quasi-Functional (Note 1) Fully Operational Supply Current Normal Mode (IDD + IPWR) (All Switches Open) Supply Current Sleep State (IDD(SS) + IPWR(on)) Supply Current Periodic Mode (Polling at 30-50 ms period) (All Switches Open) Logic Supply Voltage Bandgap Voltage Output Pin (Tested with 130 kW 0.1% resistor) VDD VBG V VPWR(qf) VPWR(fo) IPWR(on) I(ss) 5.5 7.0 - - - 4.75 1.18 - - 100 2.0 26 - 1.26 7.0 26 300 10 - 5.25 1.4
mA mA mA
V V
SWITCH INPUT
Pulse Wetting Current Switch to Battery Pulse Wetting Current Switch to Ground Sustain Current Switch to Battery Sustain Current Switch to Ground Tri-State Input Current Switch Detection Threshold Switch Input Voltage Range Iw(batt) Iw(gnd) Is(batt) Is(gnd) IT(swt) Ith Vin 7.5 -7.5 0.4 -0.4 -10 3.25 -14 14 -14 0.75 -0.75 - 3.75 - 25 -25 1.25 -1.25 10 4.75 40 mA mA mA mA
mA
V V
DIGITAL INTERFACE
Input Logic Voltage Thresholds (Note 2) SO High State Output Voltage (IOH = 1 mA) SO Low State Output Voltage (IOL = 1 mA) SO Tri-State Leakage Current (CSB = 0.7 VDD, VSO = 0 to VDD) SI Pull-Down Current (SI = VDD) SCLK Input Current (0 V = VDD) CSB Pull-Up Current (CSB = 0 V) RSTB Pull-Down Current (RSTB = 0 V) INTB Low State Output Voltage (IOL = 0.5 mA) Input Capacitance on SCLK, SI, Tri-State SO, CSB (Note 3) VIN(logic) VOH(so) VOL(so) IT(so) ISI ISCLK ICSB IRSTB VOL(INTB) CIN 0.2 * VDD 3.5 - -40 5.0 -10 -25 5.0 - - - - - - - - - - - - 0.7 * VDD - 0.4 40 35 10 -5.0 35 0.4 20 V V V
mA mA mA mA mA
V pF
NOTES: 1. SPI inputs and outputs are operational; Fault reporting may not be fully operational within this voltage range. 2. Upper and lower logic threshold voltage levels apply to SI, CSB, SCLK, RSTB, SYNC, MASL. 3. This parameter is guaranteed by design, but not production tested
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MOTOROLA TSG IC DEVICE DATA
MC33884
DYNAMIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR
16 V, -40C TC 105C, unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.)
Characteristics Symbol Min Typ Max
Units
SWITCH INPUT Pulse Wetting Current Duration Interrupt Delay Time SCLK Frequency vs. SO Load Capacitance 200 pF 160 pF 120 pF DIGITAL INTERFACE TIMING Falling Edge of CSB to Rising Edge of SCLK (Note 1) (Required Set-up Time) Falling Edge of SCLK to Rising Edge of CSB (Required Set-up Time) SI to Rising Edge of SCLK (Required Set-up Time) Rising Edge of SCLK to SI (Required Hold Time) SO to Rising Edge of SCLK (Required Set-up Time) Rising Edge of SCLK to Falling Edge of SO (Hold Time) SO Rise Time, SO Fall Time (CL = 200 pF) SI, CSB, SCLK Incoming SIgnal Rise Time (Note 2) SI, CSB, SCLK Incoming Signal Fall Time (Note 2) Time from Falling Edge of CSB to SO Low Impedance (Note 3) Time for Rising Edge of CSB to SO High Impedance (Note 4) Time from Falling Edge of SCLK to SO Data Valid (Note 5) Recovery Time for Sequential Transfers tlead tlag tSU2 tH2 tSU1 tH1 tr(SO) tf(SO) tr(SI) tf(SI) tSO(en) tSO(DIS) tvalid tREC - - - - 90 90 - - - - - - - 100 - 25 25 125 125 30 - - 80 80 65 100 140 50 45 45 - - 50 50 50 110 110 105 120 ns ns ns ns ns ns ns ns ns ns ns ns ns tpulse tINT(delay) fSCLK 30 2.5 3.2 3.5 4.0 34 - - 43 13 - ms ms MHz
NOTES: 1. This parameter is guaranteed by design, but not production tested. 2. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 3. Time required for output status data to be available for use at SO pin. 4. Time required for output states data to be terminated at SO pin. 5. Time required to obtain valid data out from SO following the falling edge of SCLK.
MOTOROLA TSG IC DEVICE DATA
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MC33884
tLEAD
CSB
tWH
fSCK
tLAG
SCLK
tWL tSOEN tSU1 tVALID tH1 tSODIS
SO
tH2 tSU2
SI
Figure 3. SPI Timing Diagram
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MC33884
CIRCUIT DESCRIPTION Introduction
The MC33884 is a monolithic integrated circuit designed to interface between external electrical system switches and low voltage microprocessors via a Serial Peripheral Interface (SPI). The MC33884 monitors the OPEN/CLOSED status of multiple external switches used in a system. The MC33884 features 4 programmable Switch-to-Ground or Battery sense inputs, 6 Switch-to-Ground sense inputs, 2 Switch-to-Battery sense inputs, programmable Wake-up Timer, programmable Interrupt Timer, and programmable wetting current settings. All inputs are protected for ESD transients when implemented with the appropriate ESD capacitor. There are numerous applications for this device in aircraft, aerospace, robotic, process & control, automotive, and security systems. Potential applications exist where switch status verification for safety, fault tolerant operation, or process control function purposes are critical. The MC33884 has four modes of operation: Sleep, Normal, Polling, and Polling + INT Timer. The MC33884 is designed to provide a robust interface between system switch contacts and a microprocessor. Each MC33884 input provides the switch contact with high levels of wetting current during switch closure. After the input switch has been closed for 20 ms, the wetting current is reduced, hence reducing power dissipation in the IC. The response to a SPI command will always return Switch Status, Master/Slave, INT Flag, and Mode settings. The following section describes the programming modes and features of the MC33884. Two or more MC33884 devices may be used in a module system when implemented in a parallel or serial configuration. Figure 5 and Figure 6 show the parallel and serial configurations respectively. When using the Serial configuration, 32 clock cycles are required for a complete transfer of data to the MC33884.
MC68HCXX Microcontroller
MOSI SI
16 Bit Shift Register
MISO SO
MC33884
SCLK Parallel Ports INT
SCLK CS RSTB INTB
SI
MC33884
SO SCLK CS RSTB INTB
Microprocessor Interface
The MC33884 directly interfaces to 3.3 or 5.0 V MCU. SPI serial clock frequencies in excess of 5.0 MHz may be used for programming and reading switch input status. Figure 4 shows the configuration between an MCU and one MC33884. Figure 5. SPI Parallel Interface with Microprocessor
MC68HCXX Microcontroller
MOSI SI
MC68HCXX Microcontroller
MOSI SI
MC33884
16 Bit Shift Register
MISO SO
MC33884
16 Bit Shift Register
MISO SO
16 Bit Shift Register
Parallel Ports
SCLK
SCLK CS RSTB
INT
INTB
SCLK Receive Buffer Parallel Ports RSTB CS INTB To Logic
SI
INT
MC33884
SO SCLK CS RSTB INTB
Figure 4. SPI Interface with Microprocessor The MC33884, though originally designed for automotive use, is very useful in a variety of other applications, i.e., computer, telecommunications, and industrial fields. It is parametrically specified over an input battery/supply voltage of 9.0 to 16.0 V but is designed to operate over a considerably wider range of 5.5 to 26.5 V.
Figure 6. SPI Serial Interface with Microprocessor
MOTOROLA TSG IC DEVICE DATA
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MC33884
PIN FUNCTIONAL DESCRIPTION CSB Pin
The system MCU selects the MC33884 to be communicated with through the use of the CSB pin. With the CSB in a logic low state, command words may be sent to the MC33884 via SI and switch status can be received by the MCU via SO. Falling edge of CSB enables the SO output, latches the state of the INTB pin, operating mode and the state of the external switch inputs. Rising edge of CSB disables the SO driver, resets the INTB pin to logic [1], activates the received command word, and allows the MC33884 to act upon new data obtained from switch inputs. To avoid any spurious data, it is essential that the high-to-low and low-to-high transition of the CSB signal occur only when SCLK is in a logic low state. Internal to the MC33884 is an active pull up on CSB.
SYNC Pin
The SYNC input is used by slave IC during Polling mode. The SYNC allows multiple MC33884 ICs to poll the multiple inputs at the same time. The Master controls the polling period. The Slave is allowed to shut down it's oscillator to conserve current. When the Slave receives the SYNC signal from the Master, the Slave starts the internal oscillator and reads the switch inputs.
INTB Pin
The INTB pin is an interrupt output from the MC33884. The INTB pin is an open drain output with an internal pull up. In normal mode a switch state change will trigger the INTB pin. The INTB pin and INT bit (flag) is latched on falling edge of CSB. This permits the MCU to determine the origin of the interrupt. The flag INT bit in the SPI word is the inverse of the INTB pin. The INTB pin is cleared on rising edge of CSB. In Polling mode the INTB pin is active only during the ON time (when sink and source currents are active).
SCLK Pin
The system clock pin (SCLK) clocks the internal 16-bit shift register of the MC33884. The serial input (SI) data is latched into the input shift register on the rising edge of SCLK signal. The serial output pin (SO) shifts the switch status bits out on the falling edge of SCLK. False clocking of the shift register must be avoided to guarantee validity of data. It is essential that the SCLK pin be in a logic low state whenever chip select pin (CSB) makes any transition. For this reason it is recommended, though not necessary, that the SCLK pin be commanded to a low logic state as long as the device is not accessed (CSB in logic high state). When the CSB is in a logic high state, any signal on the SCLK and SI pin will be ignored and the SO pin is Tri-Stated (high impedance).
RSTB Pin
The RSTB pin is active low reset input to the MC33884. When asserted, the MC33884 will reset all internal registers, timers, and enter a sleep mode (with all switch inputs in a Tri-State condition). Only an MCU SPI command word will wake the MC33884 from a sleep state. The RSTB pin may be controlled directly from a general purpose I/O pin or from a system/MCU reset.
SI Pin
This pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK. A logic high state present at SI when SCLK rises, programs a [1] into the command word on rising edge of the CSB signal. To program a complete word, 16 bits of information must be entered into the MC33884. Internal to the IC is an active pull down on the SI pin.
VBG Pin
The VBG pin requires a 130 k to ground for standard wetting and sustain currents. The device is tested with a 0.1% value, but a standard 1.0% could be used for proper functionality.
VPWR Pin
VPWR pin is battery/supply source pin for the MC33884. The VPWR pin requires external reverse battery/supply and transient protection. Maximum input voltage on VPWR is 40 volts. All wetting currents and sustain currents are derived from VPWR.
SO Pin
The serial output (SO) pin is the output from the shift register. The SO pin remains Tri-State until the CSB pin transitions to a logic low state. All "open switches" are reported as [0], all `closed switches' are reported as [1]. The negative transition of CSB will make status bit 15 available on SO. Each successive negative clock will make the next status bit available. The SI/SO shifting of the data follows a first-in-first-out protocol with both input and output words transferring the Most Significant Bit (MSB) first.
SP1 - SP4 Pins
The MC33884 has 4 switch sense inputs that may be programmed to read switch-to-ground or switch-to-battery/ supply contacts. Transient battery/supply voltages greater than 40 volts must be clamped by an external device. Surface mount 0805 MOVs and transient voltage suppressors (TVS) are available in SOT-23 packages. The sensed input is compared with an internal 4.0 volt reference. When programmed to sense switch-to-battery, sensed voltages greater than 4.0 volts are interpreted as a CLOSED switch. Sensed voltages less than 4.0 V are interpreted as an OPEN switch. The opposite holds true when inputs are programmed to sense switch-to-ground. Further programming can set the wetting currents or make the inputs Tri-State. Programming methods are provided in the following section.
MASL pin
The MASL pin is required when multiple MC33884 devices are used in one module. The MASL (Master/Slave) identifies which device will be the master and which will be the slave. Master/Slave identification is used during Polling mode. In the Polling mode the Master device has it's internal oscillator running while the Slave device oscillator is shutdown. When polling the Master device wakes the Slave via the SYNC pin. This feature provides minimal quiescent from VPWR and VDD pins.
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MOTOROLA TSG IC DEVICE DATA
MC33884
PIN FUNCTIONAL DESCRIPTION (continued) SB1, SB2 Pins
The SB pins are switch-to-battery sensing inputs only. Transient battery/supply voltages greater than 40 volts must be clamped by external device. Surface mount 0805 MOVs and transient voltage suppressors (TVS) are available in SOT-23 packages. The sensed input is compared with an internal 4.0 volts reference. Voltages greater than 4.0 volts are interpreted as a CLOSED switch. Sensed voltages less than 4.0 V are interpreted as an OPEN switch. Programming can set wetting currents or Tri-State the input. Programming methods are provided in the following section.
SG1 - SG6 Pins
The SG pins are switch-to-ground inputs only. The input is compared with the internal 4.0 volt reference. Voltages greater than 4.0 volts are interpreted as an OPEN switch. Voltages less than 4.0 V are interpreted as a CLOSED switch. Programming can set the wetting currents or Tri-State the input. Programming methods are provided in the following section.
FUNCTIONAL DESCRIPTION POWER UP
On initial power up, all MC33884 registers will be cleared and the device will enter the Sleep mode. To exit Sleep mode a valid command word is required to be received from the microprocessor. Polling mode allows the user to reduce quiescent current by disabling sink and source currents during swtich "OFF" periods.
Sleep Command
Sleep mode can be entered by a SPI Sleep command or asserting the RSTB pin. In Sleep mode all inputs are Tri-State and all internal active pull up and pull down currents are disabled. Sleep mode reduces the current drain to a quiescent current level of 10 A and disables the IC. Sleep mode provides lowest quiescent current for the IC. Exit from sleep mode requires a valid SPI RUN, TRI-STATE, or METALLIC command.
RUN Command
Run command places the IC in one of three operating modes; Normal, Polling, and Polling + INT Timer. The command also programs the SP1 to SP4 sense inputs (switch-to-battery [1] or switch-to-ground [0]). See Table 1. Normal mode is the normal operating mode of the MC33884. In Normal Mode the status of the input switches are latched on falling edge of CSB and data is sent back to MCU via SPI. All programmed combinations of source and sink currents, used for sensing purposes, are always active in this mode. In normal mode an interrupt is generated and sent to the microprocessor whenever an external switch changes its OPEN or CLOSED state. Prior to a switch closing, the MC33884 sources 0.75 mA of sustain current. When the voltage at the input crosses the comparator threshold, 14 mA of current is allowed to flow. The 14 mA wetting current shuts off after a 20 ms timer expires. Polling mode reads a switch status periodically and interrupts the microprocessor only when an external switch is sensed as being CLOSED. If the MC33884 senses all external switches to be OPEN, the Polling mode of operation continues. If a switch is sensed CLOSED, an interrupt is sent to the microprocessor and the MC33884 transfers it's operational mode to the Normal mode. The Polling mode provides a reduction in quiescent current by turning OFF all source and sink currents during sensed switch OFF periods. The
Polling + INT Timer mode of operation is similar to the Polling mode above, with the addition of an interrupt being sent to the microprocessor if a switch is sensed CLOSED or upon the internal interrupt timer "timing out". An interrupt is always ultimately sent to the microprocessor in this mode. The microprocessor can be programmed to read (or ignore) the MC33884's reported switch status upon receiving the interrupt. If a switch is sensed CLOSED, operation reverts automatically to the Normal mode. If all switches are sensed OPEN, and the wake-up timer (INT Timer) times out, the MC33884 continues to operate in the Polling + INT Timer mode. The wake-up timer duration may be set much longer than the Polling time.
TRI-STATE Command
TRI-STATE command places all switch inputs into Tri-State. All comparators on inputs are disabled in this mode. The device will return [0] for the switch status.
SPI PROGRAMMING
The MC33884 uses the SPI in full duplex synchronous slave mode for communication with the microprocessor. The MC33884 is programmed via a 16 bit word command from the MCU. The word is sent to the device with the MSB first. The command word sent to the MC33884 sets the mode of operation in the device. Data received back from the MC33884 is the status of the sensed input switch on falling edge of CSB. Sixteen clock periods are required for each transmission to be valid. After the 16 clocks, CSB is returned to the inactive state (logic [1]), command words are no longer accepted into SI, and the SO pin is Tri-Stated. The response to a SPI command returns status based on previous command word. This previous command could be a hardware reset as well as any of the other commands discussed in this section.
MOTOROLA TSG IC DEVICE DATA
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MC33884
PROGRAMMING AND CONFIGURATION DESCRIPTION
SPI Commands from Microcontroller Command Protocol (Data into SI) Table 1: SPI Command Protocol
MSB Bit Command Sleep [DEFAULT] Run Tri-State Metallic IC Test Mode RESET VALUES: Run Register Tri-State Register Metallic Register -- -- -- -- -- -- -- -- -- -- -- -- U 0 U U 0 U U 0 U U 0 U U 0 U U 0 U U 0 U U 0 U U 0 U U 0 U U 0 U U 0 U 16 0 0 0 0 1 15 0 0 0 1 X 14 0 0 1 0 X 13 0 1 1 1 X 12 X MOD2 TG6 MG6 X 11 X MOD1 TG5 MG5 X 10 X ST3 TG4 MG4 X 9 X ST2 TG3 MG3 X 8 X ST1 TG2 MG2 X 7 X - TG1 MG1 X 6 X WT2 TP4 MP4 X 5 X WT1 TP3 MP3 X 4 X CP4 TP2 MP2 X 3 X CP3 TP1 MP1 X 2 X CP2 TB2 MB2 X LSB Bit 1 X CP1 TB1 MB1 X
U: Unknown value coming out of Sleep mode; must configure with Run and Metallic commands. NOTE: the remaining combinations of Bits [16:13] are NON-FUNCTIONAL (0010, 0100, 0110, 0111) LABEL DEFINITIONS MOD[2:1] CP[4:1] TG[6:1] TB[2:1] TP[4:1] Operating Mode Configure Programmable Switch Tri-State Switch-to-Ground Tri-State Switch-to-Battery Tri-State Programmable Switch ST[3:1] WT[3:1] MG[6:1] MB[2:1] MP[4:1] Sample OFF Time Wake-Up Time Metallic Switch-to-Ground Metallic Switch-to-Battery Metallic Programmable Switch
Sleep Command
The Sleep command places the IC in Sleep mode and essentially turns off the part. By definition, a hardware reset sends/keeps the IC in Sleep mode. All inputs are Tri-Stated, disabling all input blocks and all internal pull-ups/pull-downs. Only a SPI command can take the IC out of Sleep mode. Exiting this mode requires a valid Run, Tri-State, or Metallic command.
MSB Bit Command Sleep [DEFAULT] 16 0 15 0 14 0 13 0 12 X 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X LSB Bit 1 X
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MOTOROLA TSG IC DEVICE DATA
MC33884
DESCRIPTION (Continued) Run Command
The Run command gives access to all of the operating modes: Normal, Polling, and Polling + INT Timer. It allows selection of tWAIT and tWAKE, and configures the programmable input blocks. Bit 7 is currently unused. Note that the Run register values are unknown after exiting the Sleep mode.
MSB Bit Command Run RESET VALUES: Run Register -- -- -- -- U U U U U U U U U U U U 16 0 15 0 14 0 13 1 12 MOD2 11 MOD1 10 ST3 9 ST2 8 ST1 7 - 6 WT2 5 WT1 4 CP4 3 CP3 2 CP2 LSB Bit 1 CP1
U: Unknown value coming out of Sleep mode; must configure with Run command.
MOD[2:1] -- Operating Mode In the Run command, the two MOD bits place the device in one of three operating modes: Normal, Polling, and Polling + INT Timer. Bit Definitions for Run Command COMMAND: Run (0001), with bits[12:1] as follows
MODE Undefined Normal Polling Polling + INT Timer MOD2 0 0 1 1 MOD1 0 1 0 1 ST[3:1] XXX XXX ST[3:1] ST[3:1] WT[2:1] XX XX XX WT[2:1] CP[4:1] XXXX CP[4:1] CP[4:1] CP[4:1]
ST[3:1] -- OFF Time between Samples (tWAIT) During both Polling modes (with and without INT Timer 'Wake-Up', MOD2=[1]), these bits select the interval of time (tWAIT) that the Input Blocks are turned OFF; switch transitions are not detected during the OFF interval. Sample OFF Time Prescales
ST[3:1] 000 001 010 011 100 101 110 111 Multiplier Selected 5 9 17 25 33 41 49 57 OFF Time, tWAIT (ms) [tDETECT (4.8ms typ.) * Multiplier] 15 - 25 30 - 55 60 - 90 100 - 140 145 - 185 195 - 215 220 - 245 250 - 320 ON Time (ms) 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3
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MC33884
DESCRIPTION (Continued)
WT[2:1] -- Wake-Up Time These bits let the device assert an external interrupt (INTB) at the following intervals during Polling mode (MOD2=MOD1=1). Wake-Up Delay Prescales
WT[2:1] 00 01 10 11 Multiplier Selected 512+1 256+1 128+1 64+1 Wake-Up Interrupt, tWAKE (ms) [tDETECT (2.8ms typ.) * Multiplier] 2400 - 3200 1200 - 1600 600 - 750 290 - 360
CP[4:1] -- Configure Programmable Switch Configure the programmable inputs SP[4:1] to detect either an external switch-to-ground (internal current source) or an external switch-to-battery (internal current sink). Note that this configuration may be entered in any of the three valid Operating Modes (see MOD[2:1]) within the Run command. Programmable Switch Bit Definition
CPx 0 1 External Switch to: Ground Battery
Tri-State Command
This command places an external switch into a "Tri-State" condition, essentially disconnecting the wetting current (if the switch is metallic) and the sustain current. The internal input-threshold comparator is still internally connected to its external pin. This command does not change the mode of operation (e.g., a Tri-State command received while in Polling mode leaves the part in that mode). Note that the Tri-State register clears all bits to [0] (all inputs in Tri-State) in response to a hardware reset; all inputs also remain in Tri-State after exiting the Sleep mode.
MSB Bit Command Tri-State RESET VALUES: Tri-State Register -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 16 0 15 0 14 1 13 1 12 TG6 11 TG5 10 TG4 9 TG3 8 TG2 7 TG1 6 TP4 5 TP3 4 TP2 3 TP1 2 TB2 LSB Bit 1 TB1
TG[6:1] -- Tri-State Switch-to-Ground TB[2:1] -- Tri-State Switch-to-Battery TP[4:1] -- Tri-State Programmable Switch
Tri-State Bit Definition
TGx, TBx, TPx 0 1 Input Configured to: Input Disabled [DEFAULT] Input Enabled
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MC33884
DESCRIPTION (Continued) Metallic Command
This command enables the pulsed wetting current for an external metallic switch and disables it for an external non-metallic switch. This command does not change the mode of operation (e.g., a Metallic command received while in Polling mode leaves the part in that mode). Note that the Run register values are unknown after exiting the Sleep mode.
MSB Bit Command Metallic RESET VALUES: Metallic Register -- -- -- -- U U U U U U U U U U U U 16 0 15 1 14 0 13 1 12 MG6 11 MG5 10 MG4 9 MG3 8 MG2 7 MG1 6 MP4 5 MP3 4 MP2 3 MP1 2 MB2 LSB Bit 1 MB1
U: Unknown value coming out of Sleep mode; must configure with Metallic command. MG[6:1] -- Metallic Switch-to-Ground MB[2:1] -- Metallic Switch-to-Battery MP[4:1] -- Metallic Programmable Switch
Metallic Switch Bit Definition
MGx, MBx, MPx 0 1 Accepted Switch Type: Non-metallic Metallic (enable wetting current pulse)
Test Mode
Bit 16 is reserved for placing the device into a special IC Test mode. It is used to confirm various internal functions.
MSB Bit Command IC Test Mode 16 1 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X LSB Bit 1 X
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MC33884
DESCRIPTION (Continued)
SPI Responses
Response Protocol (Data out of SO) Table 1: SPI Response Protocol
MSB Bit Mode Reset/Sleep Normal Polling Polling + INT Timer 16 0 0 1 1 15 0 1 0 1 14 X MASL MASL MASL 13 X INT X INT 12 X SG6 SG6 SG6 11 X SG5 SG5 SG5 10 X SG4 SG4 SG4 9 X SG3 SG3 SG3 8 X SG2 SG2 SG2 7 X SG1 SG1 SG1 6 X SP4 SP4 SP4 5 X SP3 SP3 SP3 4 X SP2 SP2 SP2 3 X SP1 SP1 SP1 2 X SB2 SB2 SB2 LSB Bit 1 X SB1 SB1 SB1
LABEL DEFINITIONS SG[6:1] SB[2:1] SP[4:1] Switch-to-Ground Flag Switch-to-Battery Flag Programmable Switch Flag MASL INT Master/Slave Identification Flag External Interrupt Flag
Reset/Sleep
When the Reset (RSTB) input is active (logic [0]), all internal registers are cleared, thereby placing the device in Sleep mode and upon the RSTB input returning to the inactive state (logic [1]) the MC33884 remains in Sleep mode. A SPI command, received from the microprocessor, is necessary to command the device out of Sleep mode.
MSB Bit Mode Reset/Sleep 16 0 15 0 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X LSB Bit 1 X
Note: The SPI response given while sending the command to exit Sleep mode should be ignored due to unknown power-up state.
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MC33884
DESCRIPTION (Continued)
Normal and Periodic
Bits [16:15] identify one of the three operating modes: Normal, Polling, and Polling + INT Timer. The remaining bits identify the device as the Master or a Slave, whether the device has an interrupt that has not been cleared, and the state of all the inputs.
MSB Bit Mode Normal Polling Polling + INT Timer 16 0 1 1 15 1 0 1 14 MASL 13 INT X INT 12 SG6 11 SG5 10 SG4 9 SG3 8 SG2 7 SG1 6 SP4 5 SP3 4 SP2 3 SP1 2 SB2 LSB Bit 1 SB1
MASL -- Master/Slave Identification Flag
This flag is the same as the state of the MASL pin. It provides software identification of the configuration of each IC. MASL Bit Definition
MASL 0 1 Device is a Slave Master
INT -- External Interrupt Flag
This flag identifies this particular IC as the initiator of an external interrupt. It is the inverse of INTB. INT Bit Definition
Mode Normal Bit 16 0 15 1 14 X 13 0 1 Polling Polling + INT Timer Ti 1 1 0 1 X X X 0 1 Type of Interrupt Nothing has happened Switch Interrupt - Nothing has happened Wake-Up Interrupt
SG[6:1] -- Switch-to-Ground Flag SB[2:1] -- Switch-to-Battery Flag SP[4:1] -- Programmable Switch Flag
These twelve flags indicate the state of all switch inputs: Switch State Bit Definition
SGx, SBx, SPx 0 1 External Switch is: Open Closed Mode Normal Polling Input States Latched: At the moment CSB transitions to logic 0.
Tri-State
All Tri-State inputs have their wetting and sustain currents disabled. By definition, all disabled inputs return the following value for the switch state whenever SPI data is exchanged: Tri-State Bit Definition
SGx, SBx, SPx 0 External Switch is: Tri-State
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MC33884
PACKAGE DIMENSIONS
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
CASE 751E-04 ISSUE E
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MOTOROLA TSG IC DEVICE DATA
MC33884
NOTES
MOTOROLA TSG IC DEVICE DATA
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MC33884
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E
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MOTOROLA TSG IC DEVICE DATA
MC33884/D
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